1. Field of the Invention
The present invention relates to a method for producing a semiconductor device and a semiconductor device.
2. Description of the Related Art
The degree of integration of semiconductor integrated circuits, in particular, integrated circuits using MOS transistors has been increasing. With this realization of high integration, MOS transistors used in such integrated circuits have been miniaturized to the nano-scale.
With the progress of such miniaturization of MOS transistors, it becomes more difficult to suppress a leak current and it may become more difficult to reduce the area occupied by circuits from the standpoint of the requirement of ensuring a necessary amount of current.
In order to address this problem, a surrounding gate transistor (hereinafter referred to as “SGT”) has been proposed in which a source, a gate, and a drain are arranged in a direction perpendicular to a substrate, and a gate electrode surrounds a pillar-shaped semiconductor layer (silicon pillar) (refer to, for example, Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761).
Hitherto, an SGT has been produced as follows. A silicon pillar on which a hard mask composed of a nitride film is formed so as to have a pillar shape is formed by using a first mask for drawing a silicon pillar. Furthermore, a planar silicon layer is formed on a bottom portion of the silicon pillar by using a second mask for drawing a planar silicon layer. Furthermore, a gate line is formed by using a third mask for drawing a gate line (refer to, for example, Japanese Unexamined Patent Application Publication No. 2009-182317). That is, a silicon pillar, a planar silicon layer, and a gate line are formed by using three masks.